1. Field of the Invention
The present invention relates to an interface system for performing data transfer, and more particularly to a data input/output circuit which is preferably used for performing data transfer at high speed in an interface system and uses a reference voltage and a clock as differential inputs to operate in synchronization with the clock.
2. Description of the Prior Art
In recent years, with faster processing of CPU (Central Processing Unit), increasingly faster processing is achieved also in memory devices as typified by RDRAMs (Rambus(trademark) DRAM (Dynamic Random Access Memory)), SLDRAM (SyncLink(trademark) DRAM) or the like.
Schemes which independently use a clock for data input and a clock for data output have been proposed in Rambus(trademark) interfaces or SyncLink(trademark) interfaces for realizing fast data transfer between the CPU or its peripheral circuits and these memory devices.
FIG. 1 is a block diagram showing a configuration of a conventional interface system which independently uses a clock for data input and a clock for data output. As shown in FIG. 1, in such an interface-system, master device 1 manages data transfer between master device 1 and a plurality of slave devices (only two slave devices 21, 22 are shown in FIG. 1).
A clock for input and a clock for output are provided from clock generating circuit 4 to each of master device 1 and the plurality of slave devices 21, 22. Since data is typically transferred at a high rate of 500 MHz to 1 GHz on bus 5 connecting master device 1 with slave devices 21, 22, terminating device 3 is connected at the end of bus 5 for providing impedance matching of bus 5 and reducing distortion in waveform of the transferred signal.
Each of slave devices 21, 22 comprises a data input/output circuit for transmitting and receiving data in synchronization with the clock for input and the clock for output. The data input/output circuit receives data in synchronization with each of a rising edge and a falling edge of the clock for input, and transmits data in synchronization with each of a rising edge and a falling edge of the clock for output. Single reference voltage VREF, which serves as a reference for determining a High level and a Low level in the clock for input and the clock for output, is provided to the data input/output circuit included in each of slave devices 21, 22. Reference voltage VREF is typically provided from master device 1, for example by dividing power supply voltage VDD using resistances.
FIG. 2 is a block diagram showing an example of a configuration of the above-mentioned data input/output circuit. As shown in FIG. 2, the data input/output circuit comprises PLL (phase locked loop) circuit for input clock 11 for using reference voltage VREF and the clock for input as differential inputs to generate therefrom an internal clock for input to be used within the device; PLL circuit for output clock 12 for using reference voltage VREF and the clock for output as differential inputs to generate therefrom an internal clock for output to be used within the device; first flip flop 13 and second flip flop 14 for synchronizing input data received through bus 5 and the internal clock for input; and selector circuit 15 for switching and outputting internal output data from within the device in synchronization with the internal clock for output.
PLL circuit for input clock 11 and PLL circuit for output clock 12 have the same circuit configuration, an example of which is shown in FIG. 3. When the circuit is simply called a PLL circuit, it refers hereinafter to both PLL circuit for input clock 11 and PLL circuit for output clock 12.
As shown in FIG. 3, the PLL circuit comprises first clock amplifier 31 for shaping clock waveform using the clock and the reference voltage VREF which are differentially supplied thereto; variable delay circuit 32 for adjustably delaying the phase of an output clock from first clock amplifier 31; clock driver 33 for increasing the driving ability of an output clock from variable delay circuit 32; and phase comparison circuit 36. Phase comparison circuit 36 comprises second clock amplifier 34 for shaping clock waveform using the clock and the reference voltage VREF which are differentially supplied thereto; and phase difference detecting circuit 35 for comparing the phase of an output clock from second clock amplifier 34 and the phase of an output clock from clock driver 33 to output a delay adjusting signal for changing the phase in variable delay circuit 32 in accordance with the comparison result. The output clock of clock driver is an internal clock for input (or an internal clock for output).
The PLL circuit is a circuit for providing a clock having the same phase as that of the clock for input (or the clock for output), to be accurate, a clock with one cycle delay, to the inside of the device. The use of such a PLL circuit enables cancellation of delay of the clock amplifier itself.
However, when the data input/output circuit receives data, it is necessary for reliable reception of data to establish a value of data at the time of a rising or falling edge of a clock and to hold the value of data for a predetermined time period to acquire the established data. Typically, a time period taken for establishing data is called setup time ts, while a time period for holding necessary data is called hold time tH.
In the conventional interface system for performing fast data transfer as described above, requirement becomes greater for the timing in passing data with respect to a clock. For example, when a slave device receives data, as shown in FIG. 4A, if data is outputted from a master device at a time delayed by tQM with respect to the clock for input, a problem occurs that the slave device can not receive the data since the timing of data reception with respect to the clock for input is not sufficient for setup time tS required for receiving data. When a slave device transmits data, as show in FIG. 4B, if the slave device transmits the data at a time delayed by tQS with respect to the clock for output, a problem occurs that the master device can not receive the data since the timing of data reception with respect to the clock for output is not sufficient for setup time tS required for receiving data.
It is a first object of the present invention to provide a data input/output circuit which solves the problems as described above inherent in the prior art and which can set reception timing of input data to an optimum value.
It is a second object of the present invention to provide an interface system having such a data input/output circuit.
The first object of the present invention is achieved by a data input/output circuit for transmitting and/or receiving data in synchronization with a supplied clock, comprising: a circuit for differentially receiving the clock and a reference voltage; a register for storing setting data for changeably setting a level of the reference voltage; and a level shift circuit for setting the level of the reference voltage to be supplied to the circuit to a predetermined value in accordance with the setting data stored in the register.
In the present invention, the circuit is typically a phase locked loop (PLL) circuit for generating an internal clock having a predetermined phase delay with respect to the supplied clock.
The second object of the present invention is achieved by an interface system comprising: a master device for managing data transfer; a plurality of slave devices, each of which having the aforementioned data input/output circuit for performing data transfer with the master device in accordance with instructions from the master device; and an interface line for transmitting the setting data from the master device to the slave devices.
In the data input/output circuit arranged as described above, since the clock and the reference voltage are differentially supplied, the phase of the outputted internal clock is optimally adjusted by changing the setting data stored in the register to change the value of the reference voltage. Therefore, it is possible to ensure a required setup time at reception timing of data. For this reason, even when data is transmitted with delay to the clock, the data can be reliably received. Additionally, according to the present invention, data can be reliably received in an interface system for performing data transfer using a clock for input and a clock for output independently of the clock for input.
The above and other objects, features, and advantages of the present invention will become apparent from the following description referring to the accompanying drawings which illustrate examples of preferred embodiments of the present invention.